Category Archives: VoCore

VoCore2: OpenWrt 19.07.3 Firmware

Now official OpenWrt 19.07.3 firmware released.

Link: http://vonger.cn/misc/vocore2/20200811.19073.bin (For VoCore2)

Link: http://vonger.cn/misc/vocore2/20200812.19073.bin (For VoCore2 Ultimate)

Different is VoCore2 Ultimate has embed SD card driver, for VoCore2 do not have SD card slot, it will show a lot of junk message to the system log.

Embed software:

  • LuCI
  • mem (for /dev/mem access)

Support interface:

  • SD Card (V2U)
  • Ethernet
  • WiFi
  • I2C
  • I2S
  • GPIO
  • Reference Clock
  • SPI
  • USB 2.0 HS Host

MT76: Learning…2

After read the mt76 source code, I find the source code miss eerpom 0x34 setting (not a real eeprom, just flash factory partition), and 0x34 is used to choose antenna number…

So fix is pretty simple:

--- a/mt7603/init.c
+++ b/mt7603/init.c
@@ -277,6 +277,9 @@ mt7603_init_hardware(struct mt7603_dev *dev)
        if (ret < 0)
                return ret;
 
+       if (((u8*)dev->mphy.eeprom.data)[MT_EE_NIC_CONF_0] == 0x11)
+               dev->mphy.antenna_mask = 1;
+
        ret = mt7603_dma_init(dev);
        if (ret)
                return ret;

Once we find 0x34(MT_EE_NIC_CONF_0) is 0x11, force the driver use one antenna. That’s all.

Now after over 1 hour test, this mt76 driver is working very well and stably at >= 52Mbps 1T1R.

MT76: Learning…

Develop on a chip like MT7628 is full of adventure…For new version of firmware I plan to use opensource MT76 driver instead of MT7628 driver. Weird thing is MT76 works well on some devices, but not well on some others, include VoCore2.

I guess it is antenna issue, because for normal WIFI4 routers default has two antennas works at same time for 300Mbps, 802.11n mode; but for VoCore2, default antenna 2 is disabled to save power and avoid cross talk when no second antenna attached.

Thanks to github MT76 contributors, I have some clues to fix this: https://github.com/openwrt/mt76/issues/423

After apply that patch, change mt76-2020-03-10-08054d5a/mt7603/init.c line 538

- dev->mt76.antenna_mask = 1;
+ dev->mt76.antenna_mask = 3;

I get a good result, 5minute no disconnect anymore.

...
[  5] 297.00-298.00 sec  6.31 MBytes  52.9 Mbits/sec                  
[  5] 298.00-299.00 sec  6.38 MBytes  53.5 Mbits/sec                  
[  5] 299.00-300.00 sec  6.41 MBytes  53.7 Mbits/sec                  
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-300.00 sec  1.75 GBytes  50.2 Mbits/sec                  sender
[  5]   0.00-300.07 sec  1.75 GBytes  50.2 Mbits/sec                  receiver
It stay at MCS Index: 7, do not jump to MCS Index: 15, so the two antennas will not crosstalk to each other, now we have stable result.

So this should be the solution, just need test more. Currently we store 1T1R and 2T2R parameter to factory setting partition in flash, so there are two ways, one is to add factory setting patch to change it, another is to add DTS setting patch to change it, emm, which way is better? hard choice.

To be continue…

VoCore2 + Touch + LVGL DEMO

LVGL new demo looks better

Here is the compressed firmware link http://vonger.cn/misc/screen/20200628.touch.bin.xz, upgrade then it is able to work directly πŸ™‚ Just need two files to work, one is the fbusb.ko driver for touch and USB data transfer, another is /root/demo which is the littlevgl demo application.

New Screen with touch API is simpler, please check https://vocore.io/screen.html for more details.

VoCore2 SPI: full duplex

mt7628a has a wafer/silicon bug on SPI, we can not use its SPI in full duplex mode, but we can use bitbang for that mode. For some device do not support half-duplex, maybe this is the only way.

To enable bitbang on VoCore2, we need to modify Linux kernel code, VOCORE2.DTS and kernel setting.

Setup Kernel Setting

  1. call “make kernel_menuconfig”
  2. In menu, select “Device Drivers” => “SPI Support” => <*> Β  GPIO-based bitbanging SPI Master

VOCORE2.dts

This file is in target/linux/ramips/dts, example of the DTS. We need to set the driver to “spi-gpio” and pinctrl set the pins to GPIO mode.

/dts-v1/;

#include "VOCORE2.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "vocore,vocore2", "mediatek,mt7628an-soc";
	model = "VoCore2";

	gpio-leds {
		compatible = "gpio-leds";

		status {
			label = "vocore2:fuchsia:status";
			gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		};
	};

	spi1: spi-gpio {
		status = "okay";

		compatible = "spi-gpio";

		gpio-sck = <&gpio0 7 1>;
        	gpio-miso = <&gpio0 9 1>;
        	gpio-mosi = <&gpio0 8 1>;

        	cs-gpios = <&gpio0 10 1>, <&gpio0 6 1>;
        	num-chipselects = <2>;
	};
};

&pinctrl {
        state_default: pinctrl0 {
                spi {
                        ralink,group = "spi";
                        ralink,function = "gpio";
                };
                spi_cs1 {
                        ralink,group = "spi cs1";
                        ralink,function = "gpio";
                };
        };
};

&i2c {
	status = "okay";
};

&spi1 {
	m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;
		m25p,chunked-io = <32>;

		partition@0 {
			label = "u-boot";
			reg = <0x0 0x30000>;
			read-only;
		};

		partition@30000 {
			label = "u-boot-env";
			reg = <0x30000 0x10000>;
			read-only;
		};

		factory: partition@40000 {
			label = "factory";
			reg = <0x40000 0x10000>;
			read-only;
		};

		partition@50000 {
			label = "firmware";
			reg = <0x50000 0xfb0000>;
		};
	};

	spidev@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "rohm,dh2228fv";
		reg = <1>;
		spi-max-frequency = <10000000>;
	};
};

Patch Linux spi-gpio.c

This is because CS1 pins has a default pull low resistor. If we do not patch it, CS1 will be low at startup, conflict with the flash driver who use CS0. So we must at startup setup CS1 pin to output and value to high.

                if (!SPI_N_CHIPSEL)
                        spi_gpio->cs_gpios[0] = SPI_GPIO_NO_CHIPSELECT;
                else
                        for (i = 0; i < SPI_N_CHIPSEL; i++) {
                                status = of_get_named_gpio(np, "cs-gpios", i);
                                if (status < 0) {
                                        dev_err(&pdev->dev,
                                                "invalid cs-gpios property\n");
                                        goto gpio_free;
                                }
                                spi_gpio->cs_gpios[i] = status;

+                               gpio_request(status, dev_name(&pdev->dev));
+                               gpio_direction_output(status, 1);
+                               gpio_free(status);
                        }
        }
#endif

        spi_gpio->bitbang.master = master;
        spi_gpio->bitbang.chipselect = spi_gpio_chipselect;

That is all πŸ™‚ Now the firmware is able to support SPI device in full duplex mode.

Submit patch for OpenWrt on Github

Git is good, but for beginner like me, always feeling no way to give the first bite. I am confused about fork, branch, signed-off-by, push, merge and many other commands, maybe it is pretty clear for the clever boys but not for me. Thanks to adrianschmutzler comment at https://github.com/openwrt/openwrt/pull/3022, I start to understand how it works.

Tutorial

  1. click the “Fork” button on github.com/openwrt/openwrt
  2. goto your forked openwrt, click on “Clone or download”, get the address and clone to your local.
  3. make the change on your local source code.
  4. setup your name and email on your local by command git config –global user.email xxxx@xxxxx.xxx and git config –global user.name “your name”
  5. submit your change by command “git commit -s“, remember to keep that Signed-off-By line and add the reason of the changes to comment.
  6. push the commit by command “git push origin
  7. finally, go to github, create a merge request.

Signed-Off-By is just a text line in the comment to tell other who submit that patch, I am confused about that a long time, I thought it is added by some magic :p

PS: In old good time I only use git init, git commit and git clone. Now good new day comes.

VoCore2: OpenWrt 19.07.2

Recently I try latest stable version openwrt, looks like the open source MT76 driver is much stable and fast now.

iperf3 -c 192.168.1.1
Connecting to host 192.168.1.1, port 5201
[  5] local 192.168.1.231 port 60121 connected to 192.168.1.1 port 5201
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-1.00   sec  5.33 MBytes  44.7 Mbits/sec                  
[  5]   1.00-2.00   sec  5.50 MBytes  46.1 Mbits/sec                  
[  5]   2.00-3.00   sec  5.34 MBytes  44.7 Mbits/sec                  
[  5]   3.00-4.00   sec  4.67 MBytes  39.3 Mbits/sec                  
[  5]   4.00-5.00   sec  5.47 MBytes  45.8 Mbits/sec                  
[  5]   5.00-6.00   sec  5.03 MBytes  42.3 Mbits/sec                  
[  5]   6.00-7.00   sec  4.93 MBytes  41.3 Mbits/sec                  
[  5]   7.00-8.00   sec  5.07 MBytes  42.6 Mbits/sec                  
[  5]   8.00-9.00   sec  4.95 MBytes  41.5 Mbits/sec                  
[  5]   9.00-10.00  sec  5.13 MBytes  43.0 Mbits/sec                  
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate
[  5]   0.00-10.00  sec  51.4 MBytes  43.1 Mbits/sec                  sender
[  5]   0.00-10.09  sec  51.3 MBytes  42.7 Mbits/sec                  receiver

iperf Done.

This is good πŸ™‚ Next firmware will base on this driver and I do not have to patch it anymore.

VoCore2: About Pin Share

Pin share or I call it pinmux, it is a common feature of most MCU chips. Normally a pin we can use it as GPIO or some special functions.

In picture, the orange number is each pins GPIO number. And in the color block, there is its special function.

Here is a table from vocore.io/v2.html, for example, the pin 29 on the chip has three functions, one is used as GPIO, one is system reference clock, final one is SDcard CLK.

LeftNameMuxNote
+3.3VO+3.3V outputmax output current 100mA
30TXD0GPIO12, UART0 Lite TXDpull down to GND, Test/Normal mode pin.
31RXD0GPIO13, UART0 Lite RXD3.3V
29REFCLKGPIO11, reference clock, SDXC CLK*
33P0RP10/100 PHY Port #0 RXP
34P0RN10/100 PHY Port #0 RXN
35P0TP10/100 PHY Port #0 TXP
36P0TN10/100 PHY Port #0 TXN
43TXD210/100 PHY Port #1 TXN, GPIO15, PWM Channel, SPI Slave Clock
44RXD210/100 PHY Port #1 TXP, GPIO14, PWM Channel, SPI Slave Chip Select
40PWM010/100 PHY Port #1 RXN, GPIO17, UART2 Lite TXD, SPI Slave MOSI4.7K pull down to GND
42PWM110/100 PHY Port #1 RXP, GPIO16, UART2 Lite RXD, SPI Slave MISO
45P2RP10/100 PHY Port #2 RXP, GPIO18, PWM Channel
46P2RN10/100 PHY Port #2 RXN, GPIO19, PWM Channel
47P2TP10/100 PHY Port #2 TXP, GPIO20, PWM Channel
48P2TN10/100 PHY Port #2 TXN, GPIO21, PWM Channel
49SD WPGPIO22, 10/100 PHY Port #3 TXP, SDXC WP
50SD CDGPIO23, 10/100 PHY Port #3 TXN, SDXC CD
TopNameMuxNote
GNDGroud
28SPI CS0SPI Master Chip Select 04.7K pull up to 3.3V
25SPI CLKSPI Master Clock4.7K pull up to 3.3V
26SPI MISOSPI Master In Slave Out
27SPI MOSISPI Master Out Slave In4.7K pull down to GND
24SPI CS1SPI Master Chip Select 14.7K pull down to GND
21I2C SDGPIO5, I2C Data, SDXC D2*4.7K pull up to 3.3V
20I2C CLKGPIO4, I2C Clock, SDXC D3*4.7K pull up to 3.3V
19I2S CLKGPIO3, I2S Bit Clock, SDXC CMD*
18I2S WSGPIO2, I2S L/R Clock, SDXC D0*
16I2S SDIGPIO0, I2S Data In, SDXC D1*
17I2S SDOGPIO1, I2S Data Out4.7K pull down to GND
RightNameMuxNote
GNDGround
148RXD1GPIO12, UART1 Lite RXD
147TXD1GPIO13, UART1 Lite TXDpull up to 3.3V, GPIO/JTAG mode pin
141GPIO41GPIO41, JTAG TMSJTAG needs 10K pull up, R9 -> R6
140GPIO40GPIO40, JTAG ClockJTAG needs 10K pull up, R9 -> R6
139GPIO39GPIO39, JTAG ResetJTAG needs 10K pull up, R9 -> R6
143GPIO43GPIO43, JTAG TDOJTAG needs 10K pull up, R9 -> R6
142GPIO42GPIO42, JTAG TDIJTAG needs 10K pull up, R9 -> R6
138RSTReset, touch GND to reset
137GPIO38GPIO38
136GPIO37GPIO37
+3.3VO+3.3V outputmax output current 100mA
GNDGround
GNDGround
+1.8VO+1.8V outputmax output current 100mA
BottomNameMuxNote
GNDGround
51SD D1GPIO24, 10/100 PHY Port #3 RXP, SDXC D1
52SD D0GPIO25, 10/100 PHY Port #3 RXN, SDXC D0
54SD CLKGPIO26, 10/100 PHY Port #4 RXP, SDXC CLK
55SD CMDGPIO27, 10/100 PHY Port #4 RXN, SDXC CMD
56SD D3GPIO28, 10/100 PHY Port #4 TXP, SDXC D3
57SD D2GPIO29, 10/100 PHY Port #4 TXN, SDXC D2
+3.3VO+3.3V outputmax output current 100mA
61USB DPUSB2.0 Data+
62USB DMUSB2.0 Data-
+5.0VI+5.0V inputmin input current 500mA
+5.0VI+5.0V inputmin input current 500mA
GNDGround
GNDGround
MiddleNameMuxNote
133PCI CKPPCI Express External Reference Clock Output+
132PCI CKNPCI Express External Reference Clock Output-
130PCI RXNPCI Express Differential Receiver RX-
129PCI RXPPCI Express Differential Receiver RX+
GNDGround
127PCI TXPPCI Express Differential Transmit TX+
126PCI TXNPCI Express Differential Transmit TX-
135PCI RSTPCI Express Device Reset

On VoCore2 Ultimate, ES8388 do not need external clock because we can use VoCore2 system reference clock as its source, in most situation, that will save cost of the BOM.

Set the Pin Function

now, question come, how do we setup every pins function? Sometimes you may want use it as GPIO but sometimes we need to use as clock.

Actually it is same as other MCU(like STM32 and ATMEGA–Arduino) , we have register for every function.

Use this REFCLK pin as example, we can find on MT7628AN datasheet page 117, 2.2 System Control Section, 0x10000060 is that control register.

Its register is 1:0 two bits. (note: on this datasheet, its name is GPIO mode)

We can write 10b to this register, then it will be REFCLK mode.

and after it into REFCLK mode, we can change its frequency, at page 110, 0x1000002c register, bit 11:9 REFCLK0_RATE

And you can use same way to change other pins function πŸ™‚

Also I have a simple tool to do this, please download at vocore.io/v2.html, Directly write to memory/register Section.

VoCore2 + VoCam264: Push Video Stream

mjpeg-streamer is an easy way, but it only able to push mjpeg data, it is a waste because VoCam264 already has h264 stream inside.

So I plan to push h264 data to a RTMP server like nginx-rtmp(-module).

The first way in my mind is to use ffmpeg directly.

Just one command, and it should work: ffmpeg -re -f v4l2 -i /dev/video1 -c:v copy -f flv rtmp://192.168.0.xxx/live

My server is setup at rtmp://192.168.0.xxx/live

Note1: old version ffmpeg do not work well, I am using version 4.2.2. Currently openwrt package has ffmpeg, but it is 3.4.2, we must modify the Makefile and compile again to use latest version. I ave upload Makefile to github.com/vonger/vocore2, in utils folder.

Trying to set codec:h264 pix_fmt:none
parser not found for codec h264, packets or times may be invalid.

Note2: default Makefile will show error about parser, we need to enable h264 parser.

Then ffmpeg is able to push h264 video from camera to server.

Unfortunately, the speed is very slow and video is laggy…Maybe there is something wrong, because it works well on a Linux PC..

I have to find some other way.

My compiled ffmpeg ipk download at here: http://vonger.cn/misc/vocore2/ipk/ffmpeg/

To be continue…

VoCore2 Ultimate: AD/DA usage 2

Forget Keil, I love GCC. Makefile is enough for the ARM based chip GD32F150 πŸ™‚

Link to my source code:https://github.com/Vonger/gd32tools

To get AD values from UART2. Here is the Makefile. Source code please use project/adc1.

NAME = $(notdir $(CURDIR))
CMSIS = $(CURDIR)/../../GD32F1x0_Firmware_Library_v3.1.0/Firmware/CMSIS
PERIP = $(CURDIR)/../../GD32F1x0_Firmware_Library_v3.1.0/Firmware/GD32F1x0_standard_peripheral
TOOLCHAIN = $(CURDIR)/../../toolchain/mac/bin/arm-none-eabi

CC = $(TOOLCHAIN)-gcc
CP = $(TOOLCHAIN)-objcopy

DEFINES = -DGD32F130_150 -DUSE_STDPERIPH_DRIVER -DUSE_HSI_8M

INCLUDES = \
	-I$(CURDIR)/../core \
	-I$(CMSIS)/GD/GD32F1x0/Include \
	-I$(PERIP)/Include \
	-I$(CURDIR)

SOURCES = \
	$(CURDIR)/../core/core_cm3.c \
	$(CURDIR)/../core/startup_gd32f1x0.s \
	$(CMSIS)/GD/GD32F1x0/Source/system_gd32f1x0.c \
	$(wildcard $(PERIP)/Source/*.c) \
	$(wildcard $(CURDIR)/*.c)

OBJECTS = $(SOURCES:%.c=%.o)

CFLAGS = \
	-mcpu=cortex-m3 -mthumb -mlittle-endian -mthumb-interwork \
	-ffast-math -fdata-sections -ffunction-sections \
	-Wl,-T,$(CURDIR)/../core/gd32f150g8.ld,-Map,$(NAME).map,--gc-sections \
	-Wall -std=gnu99 -O2 $(DEFINES) $(INCLUDES) 

$(NAME): $(SOURCES)
	@$(CC) $(CFLAGS) $^ -lm -lnosys -o $(CURDIR)/$@
	@$(CP) -O ihex $(CURDIR)/$@ $(CURDIR)/$@.hex

test:
	@echo $(OBJECTS)

clean:
	@rm -f $(CURDIR)/$(NAME)
	@rm -f $(CURDIR)/$(NAME).map

GD32F1x0_Firmware_Library_v3.1.0 this library is from GigaDevice. Download here: http://vonger.cn/misc/vocore2/GD32F1x0_Firmware_Library_v3.1.0.rar; For toolchain, please check http://vonger.cn/?p=14891, I have a link there.

The library is for Keil originally. I make some patches, all changes are in project/core folder.

  • startup_gd32f1x0.s this mainly change the interrupt vector, we need the interrupt callback function name same.
  • gd32f150g8.ld this is used to create bin or hex file which is used to load into flash.

For VoCore2 Ultimate, we use internal 8M clock, so comment the line 46 #define __SYSTEM_CLOCK_72M_PLL_HXTAL and uncomment line 47 #define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 in GD32F1x0_Firmware_Library_v3.1.0/Firmware/CMSIS/GD/GD32F1x0/Source/system_gd32f1x0.c

Now we are ready to make. in adc1 folder, call make, it will create adc1.hex.

Connect BOOT pin on the dock to 3.3V pin on VoCore2, then power on them from microUSB.

Once VoCore2 ready, run gd32up to load adc1.hex. After upload done, power off it and disconnect BOOT from 3.3V (We do not export its RST pin, so have to power off to reset).

After you connect it back to power, the GD32F150 will in ADC mode, UART2 on VoCore2 is not for USB2TTL anymore, it will output ADC value to VoCore’s UART2. We can use minicom to view it at VoCore2 console, 115200, 8n1.